YEAR:
2026
EXPERIENCE:
VHDL, CPU Architecture, RTL/ASIC
RISC Processor Core
about.
A 32-bit RISC processor implemented in VHDL and synthesized for a Cyclone IV E FPGA. The design combines an 18-module datapath, an 8-operation ALU, and a custom 26-instruction ISA running at 116 MHz.
results.
Designing the CPU required resolving timing mismatches between the control unit and the datapath. Verification was completed using ModelSim simulations and TimeQuest timing analysis across three PVT corners, proving the transition from logic theory to synthesizable hardware.
